1. Field of the Invention
The invention relates generally to Fibre Channel environments and more specifically relates to a bridge apparatus and methods for interconnecting a plurality of non-Fibre Channel devices to a Fibre Channel arbitrated loop (FC-AL) through a bridge device.
2. Discussion of Related Art
Storage systems have evolved from utilizing bus parallel bus connections with host systems to high speed serial communication structures and protocols. Serial communication structures and protocols advantageously provide high-speed combined with lower cost cabling and longer distance cabling restrictions while further providing improved noise immunity as compared with costly parallel bus structure cabling. In particular, Fibre Channel media and protocols utilizing fiber optic communication media have been popular for some time. The fiber optic communication media provided high speed and substantial noise immunity as compared to any electrical coupling (parallel or serial). Fibre Channel standards are well known to those of ordinary skill in the art and documented standards for various aspects of the Fibre Channel architecture are readily available at sites such as www.t11.org.
Serial attached SCSI (SAS) and serial advanced technology attachment (SATA) communication protocols have largely supplanted Fibre Channel as the preferred media and protocols for coupling computing systems to storage devices in high performance storage area networks. SAS and SATA provide substantially lower cost alternatives to older Fibre Channel techniques while maintaining similar performance levels. Thus SAS and SATA storage devices are far more common and cost effective at present as compared to Fibre Channel storage devices.
In some storage applications where older, legacy, storage networks utilized Fibre Channel as the preferred coupling for high-performance storage networks, users may have substantial investment in the host bus adapters and other related storage network appliances used to couple host systems to the Fibre Channel storage network. Though SAS and SATA storage devices are relatively inexpensive, it is difficult in such legacy environments to justify the expense of replacing the entire Fibre Channel communication infrastructure (i.e., host bus adapters, fiber optic cabling, Fibre Channel network appliances, etc.) merely for the savings of lower cost storage devices. Some prior developments have therefore provided bridge devices for coupling SAS and SATA storage devices to a Fibre Channel network.
In Fibre Channel connectivity, one popular structure/topology is referred to as a Fibre Channel arbitrated loop (FC-AL). In such a topology, all devices are coupled in a ring or loop configuration such that information is passed from device to device until the device particularly addressed by a transaction receives the transactions and processes them. Typically in such a topology a Fibre Channel (FC) host is assigned a static reserved address (typically an address of zero) on the arbitrated loop. Such an FC host acts as a system agent to enable or bypass individual devices utilizing loop port enable (LPE) and loop port bypass (LPB) FC primitive sequences. A device that has been bypassed in the loop topology and does not participate in the transactions exchanged over the loop topology. Rather, such a bypassed device, though physically resident in the loop topology, is logically passive and ignores most Fibre Channel transactions.
In a typical FC-AL topology, each device on the loop represents a single target arbitrated loop physical address (T-ALPA). The enabling (setting a device to a non-bypassed state) or bypassing of a loop port using LPE or LPB FC primitive sequences enables or bypasses the single device corresponding to the T-ALPA address in the primitive sequence. For cost efficiency and simplicity, present-day bridging devices that allow coupling of SAS or SATA storage devices to an existing FC-AL topology utilize a single T-ALPA in the loop topology regardless of the number of physical SAS or SATA storage devices coupled with the bridge device. Other higher layer addressing mechanisms are utilized for selecting a particular SAS or SATA device through the bridge device but at the lowest layer of LPE/LPB FC primitive sequences, all devices coupled with the bridge device having a single T-ALPA would be enabled or bypassed.
To allow for each individual storage device coupled with a bridge to be individually enabled or bypassed, some prior solutions have provided software/firmware capabilities programmed to execute on a processor within the bridge device to receive the loop port enable and loop port bypass primitive sequences and attempt to enable and bypass individual devices storage devices coupled with the bridge through more complex software analysis. However, the FC primitive sequences (also known as “ordered sets”) exchanged at this lowest level are repeated in rapid succession in accordance with the FC specifications (e.g., the FC-AL specifications requires that at least three consecutive LPB/LPE primitive sequences are transmitted before a recipient acts on the received primitive sequence). Such software/firmware solutions are generally incapable of the performance required to adequately process and respond to the bypass primitive sequences received in such rapid succession in accordance with FC-AL specifications. Thus, prior software solutions are incapable of fully complying with the FC-AL specifications. Various test and real application scenarios applied to present bridge devices may fail to comply with the FC-AL specifications where, for example, a bridge device attempts to process the loop port bypass/enable sequences using software/firmware but fails to do so with adequate performance.
By way of example, in one exemplary prior art software/firmware implemented bridge solution, an FC circuit of the bridge detects receipt of an LPB primitive sequence and causes an interrupt of the general purpose processor of the bridge device to analyze and process the received LPB primitive sequence. While the processor is analyzing and processing the received primitive sequence, the FC circuit of the bridge device forces a “fill” word on the FC-AL medium to indicate an idle period while the bridge device processes a received primitive sequence. In one exemplary test, an LPB primitive sequence is sent to an FC-AL device under test immediately followed by a primitive sequence addressing the same device that was just bypassed. For example, an OPEN primitive sequence may be transmitted immediately following the LPB primitive sequence. According to FC-AL standards the device should process both the LPB and the OPEN such that the FC host would receive the OPEN primitive sequence back from the FC-AL topology as not processed by the addressed device (because it was successfully bypassed). If the software/firmware interrupt processing of a present bridge device cannot process the LPB in a timely enough fashion to update its loop port state machine (LPSM) in time to receive and forward the OPEN primitive sequence (as the device would if properly bypassed), the bridge device may not properly process the OPEN primitive sequence and thus may create an apparent error condition. Though such a test scenario may be extreme and rare in practice, it is within the specifications of the FC-AL architecture. Thus, there is no useful capability in present FC to SAS/SATA bridge devices to permit enabling or bypassing of individual SAS/SATA devices coupled with the bridge device.
Thus it is an ongoing challenge to enhance the flexibility of enabling and bypassing each of multiple non-FC storage devices coupled with an FC-AL communication medium through a bridge device.